1. Field of the Invention
The present invention relates to a semiconductor memory device having a plurality of memory blocks and, more particularly, to a dynamic random access memory device having a plurality of banks including a plurality of memory blocks.
2. Description of the Background Art
A semiconductor memory device has been improved to increase its memory capacity. Particularly, the memory capacity of a dynamic random access memory device (hereinafter referred to as DRAM) has increased from 64 Mbits to 256 Mbits. In the process of improvement, a microfabrication technique has been developed to enable the memory capacity of a semiconductor package of a given chip size to be increased by a factor of four for the next generation DRAM. However, it takes a long time to develop the next generation DRAM and, accordingly, an attempt has been made to lay out a DRAM of an intermediate capacity, say, 128 or 512 MBits on the same assembly chip as that designed for 64 or 256 MBits such as disclosed in, for example, Japanese Laid-open Patent Publication No. 11-265573, and Japanese Laid-open Patent Publication No. 11-203862.
The semiconductor memory device disclosed in the publication No. 11-265573 has eight memory blocks arranged in a three rows by three columns matrix so as to occupy respective eight of the nine areas except for a center area. In the semiconductor memory device disclosed in the publication the No. 11-203862, a bank includes a pair of memory blocks and the memory blocks of the bank are arranged on sub-regions symmetrical about the center area or on the neighboring sub-regions.
There are several problems in order to provide the semiconductor memory device having eight memory blocks as mentioned above. Accordingly, we had done a series of studies to materialize the semiconductor memory device and have resulted in the present invention.
In accordance with one aspect of the present invention, there is provided a semiconductor memory device including eight memory blocks, a first data bus, and a second data bus. The eight memory blocks are arranged at respective eight of the total nine areas defined in a three rows by three columns matrix, except for a center area. A first data bus has a plurality of data lines and linearly extends between memory blocks in the first row of the matrix and memory blocks in the second row of the matrix. A second data bus has a plurality of data lines and linearly extends between memory blocks in the second row of the matrix and memory blocks in the third row of the matrix. The eight memory blocks includes a first group of the four memory blocks arranged adjacent the first data bus and connected to the first data bus and a second group of the four memory blocks arranged adjacent the second data bus and connected to the second data bus.
Preferably, the first data bus may be for the memory block associated with a lower data buffer, the second data bus may be for the memory block associated with an upper data buffer. The eight memory blocks may have two groups each including four memory blocks associated with the lower data buffer or upper data buffer. The first group is positioned adjacent the first data bus and connected to the first data bus, and the second group is positioned adjacent the second data bus and connected to the second data bus.
More preferably, the first data bus may be for the memory block having an even column address, and the second data bus may be for the memory block having an odd column address. The eight memory blocks may have two groups each including four memory blocks having the even or odd column address. The first group is arranged adjacent the first data bus and connected to the first data bus, and the second group is arranged adjacent the second data bus and connected to the second data bus.
Preferably, the semiconductor memory device may further include a first data buffer and a second data buffer. The first data buffer is arranged within the center area adjacent memory blocks in the first row of the matrix and connected to the first data bus. The second data buffer is arranged within the center area adjacent memory blocks in the third row of the matrix and connected to the second data bus.
More preferably, the semiconductor memory device may further include a first perpendicular bus and a second perpendicular bus. The first perpendicular bus extends perpendicular to a longitudinal direction of the second data bus, and is connected between the second data bus and the first data buffer. The second perpendicular bus extends perpendicular to a longitudinal direction of the first data bus, and is connected between the first data bus and the second data buffer.
Preferably each of the first and second data buses may include a data bus equalizer. Each of the first and second data buses may have a partially enlarged width and may have data lines partially spaced.
More preferably, the eight memory blocks include four banks each having a pair of memory blocks. The one memory block of the bank is connected to the first data bus, and the other memory block is connected to the second data bus. The eight memory blocks are arranged such that four line segments connected between a pair of memory blocks have no crossing,
Further preferably, the semiconductor memory device may further include a row decoder associated with a memory block and a row controller for controlling the row decoder. The row controller is arranged within the center area adjacent the memory block.
Each pair of memory blocks of the bank may have a row controller for controlling the row decoder in common. The semiconductor memory device may further include a column decoder associated with a memory block and a column controller for controlling the column decoder. The column controller is arranged within the center area adjacent the memory block. Each pair of memory blocks of the bank may have a column controller for controlling the column decoder in common. A repeater circuit may be arranged between the column controller and the column decoder.
According to the semiconductor memory device of the present invention, the length of connection between the memory block and the data bus may be shortened, so that layout area may be reduced.